The present invention relates generally to a data distribution network (DDN). and more particularly to a an electronic warfare data distribution network such as a radar warning system. A possible non-military application of the DDN might be a large inventory system.
The importance of electronic warfare (EW) to the effectiveness of armed forces has become increasingly evident. This effectiveness must be maintained in the face of a growing increase in the radar environment density and technical sophistication of radar systems of potential enemies. In addition, infrared (IR) and laser systems are coming into use. These trends have resulted in particularly severe requirements on EW data processing. The data processing system must not only have much greater capacity, but it must be capable of executing a much more sophisticated set of algorithms than at any time in the past.
The EW processing is complicated by very high input data rates with much lower information content. Therefore, this input data must be processed to remove redundant information. The resulting data must then be further processed to derive information which can be used for self-protection of the platform. The processing involves highly flexible search and arithmetic operations on multiple data. Such operations are ideally suited to associative type processing.
The purpose of a project related to the subject invention was to determine if the very severe EW data processing requirements could be met or alleviated through proper application of parallel processing architectures. In particular, the single instruction multiple data stream type (SIMD), often referred to as associative processors was to be evaluated. In fact, the utility of associative processing techniques for EW applications was recognized during studies performed for the U.S. Air Force in the late sixties and early seventies. However, the state of the art in integrated circuit technology at that time could not provide associative processors with adequate capability to in the required package size to meet the demanding EW requirements. Consequently the existing requirements were met with a special hardwired associative type memory in the preprocessor section of the Microcomputer Array processor System MAPS) which was developed (See report AFAL-TR-78-157, titled "Microcomputer Array Processor" published by DTIC as number AD-A070 848). Now the IC technology has advanced to the level that the more flexible and capable associative processor organizations are feasible for EW applications. For example, a mil-standard airborne SIMD processor called ASPRO has been produced, and is used in the E-2C Aircraft.
A preprocessor in the Microcomputer Array processor System includes hardware to accept digitized radar pulse intercepts outputted by a receiver and correlate each intercept against an established emitter file for pulse train tracking and data filtering operations. The objective is to reduce the data rate into the multiprocessor by filtering, from the input pulse stream, those intercepts that originate from emitters which are currently being tracked by the preprocessor. This data rate reduction is essential to allow handling of a very high receiver data rate while still maintaining sufficient processing time per radar intercept in the multiprocessor to execute complex PRI (Pulse Repetition Interval) establishment algorithms. The filtering via correlation operation consists of comparing the parameters of each intercept pulse against the parameters of the emitter words stored in the preprocessor memory. Hardware hash addressing techniques are used to select that subset of the emitter file over which a particular correlation operation could be meaningful. If the intercept matches the emitter word within predetermined tolerances for each selected parameter, correlation is said to occur.
A system designed by LORAL include a preprocessor which forms a 13-bit hash address on frequency and AOA to use as a pointer to a cluster map. The cluster map, of necessity, has 8,192 (2.sup.13) entries. This map contains a pointer to the cluster track file if it is an entry to be updated. If the cluster map address is a null entry (not in track file) the preprocessor either forms a new cluster and appropriately updates the cluster map pointer or it extends an existing cluster and points to it. There are a maximum of 63 pulses per cluster. This would all be done in combinational logic.
U.S. patents of interest include U.S. Pat. No. 3,725,923 to Bosc et al, which discloses incoherent digital pulse doppler radar system with improved signal handling capacity which reduces the number of target signals which must be processed; U.S. Pat. No. 3,891,987 to Jensen, which discloses a data processing system for radar wherein all stored target information is instantaneously and continuously analyzed and displayed; and U.S. Pat. No. 3,885,224 to Klahr, which discloses a high-speed signal processing apparatus for mathematical processing of a sequence of pulse signal time functions.